#main tcl for sm3_core_top dc synth
#loaded by run_dc_synth.sh
#ljgibbs Apr. 2022


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#  Temp 
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set SM3_CORE_DIR /home/eda/workspace/sm3_core_lite/

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#  Reuse from DC Lab env 
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set_app_var alib_library_analysis_path .. ; # Common ALIB library location
define_design_lib WORK -path ./work	  ; # Location of "analyze"d files
suppress_message "LINT-99 CMD-041 TFCHK-049 TFCHK-050 TFCHK-055 TFCHK-084 MWLIBP-300 MWLIBP-301 MWLIBP-324"  ;

#  Additional Setup Files
source common_setup.tcl
source dc_setup.tcl

#  Verify Settings
echo "\n==================================="
echo "\nLibrary Settings:"
echo "search_path:             $search_path"
echo "link_library:            $link_library"
echo "target_library:          $target_library"
echo "symbol_library:          $symbol_library"
echo "mw_reference_library:    $mw_reference_library"
echo "mw_design_library:       $mw_design_library"
echo "\n==================================="

echo "\nReuse from SNPS DC LAB.\n"
echo "sm3_core_lite dc session is ready...\n"


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#  Load design and ELAB
#  TODO:load design with filelist file
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analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/src/sm3_core_top.sv >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_core/src/sm3_cmprss_ceil_comb.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_core/src/sm3_pad_core.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_core/src/sm3_expnd_core.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_core/src/sm3_cmprss_core.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_adder/src/csa_adder_3i_32b.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_adder/src/adder_32b.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/sub/sm3_adder/src/sm3_adder.v >> ./log/load_design.log
analyze -format verilog -vcs "+incdir+$SM3_CORE_DIR/inc" $SM3_CORE_DIR/inc/sm3_cfg.v >> ./log/load_design.log
elaborate sm3_core_top >> ./log/load_design.log

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#  Load constraint 
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source $SM3_CORE_DIR/impl/sdc/sm3_core_top.sdc >  ./log/load_cons.log

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#  Run synth 
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compile > ./log/run_compile.rpt

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#  Generate report 
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report_timing > ./log/timing.rpt
report_area > ./log/area.rpt
report_clocks > ./log/clocks.rpt
report_constraints > ./log/constraints.rpt
report_constraints -all_violators >> ./log/constraints.rpt

puts "Done, please check ${SM3_CORE_DIR}/impl/dc/log ."

